Module Overview
The module introduces both the syntax and application of HDL for the design of modern electronics. That would typically cover Xilinx, Mentor Graphics, and combinational and sequential circuits design.
Reassessment of the module, if required, will be by reassessment of the failed elements.
Educational Aims
To introduce students to the VHDL syntax and its latest development. The module will use the software tools from both Xilinx and Mentor Graphics to present FPGA based digital system design flow with VHDL.
Learning Outcomes
By the end of the module, students should be able to:
- LO1 Apply FPGA design flow in a commercial design package
- LO2 Use VHDL simulation in a commercial simulator
- LO3 Use synthesisable VHDL statements to design basic digital circuits
- LO4 Design VHDL testbench codes to simulate VHDL codes using a commercial simulator
- LO5 Synthesize VHDL codes and then explore implementation into a commercial development board
Assessment
- 30% Coursework: VHDL design project
- 5% Laboratory 1: Submission of laboratory exercises
- 5% Laboratory 2: Submission of laboratory exercises
- 5% Laboratory 3: Submission of laboratory exercises
- 5% Laboratory 4: Submission of laboratory exercises
- 5% Laboratory 5: Submission of laboratory exercises
- 5% Laboratory 6: Submission of laboratory exercises
- 40% Exam (2-hour): End of module exam (spring) (Assessed by end of spring semester)
Classes
- One 2-hour lecture each week for 11 weeks
- One 2-hour computing each week for 11 weeks